Currently, multi-chip module configurations are used in the packaging of semiconductor devices. A multi-chip module configuration provides for the mechanical and electrical interconnection between more than one semiconductor die in a common package. The package, in turn, is mounted to another printed circuit board referred to as a motherboard that contains other electronic systems with which the multi-chip module configuration interfaces. In some cases, semiconductor dies directly interconnect to one another. In other cases, semiconductor dies are mounted on opposing surfaces of a substrate and the semiconductor dies are electrically coupled to one another by means of traces and vias in the substrate. As the length of the substrate's traces and vias is shortened, the corresponding values of resistance, inductance, and capacitance reduce, and the efficiency of the electrical coupling between the semiconductor dies increases. Therefore, multi-chip module configurations often offer improved system performance including reduced noise, reduced power consumption, better signal integrity and power distribution, and increased bandwidth.
An example of a multi-chip module configuration 10 in which two semiconductor dies 12 and 14 are mounted on opposing surfaces 16 and 18 of a substrate 20 is illustrated in FIG. 1. The substrate includes a top surface 16 and a bottom surface 18. Also, the substrate is composed of multiple layers 22 of material that are formed by the well known processes used to create integrated circuits and printed circuit boards. The individual layers may be comprised of conductive or insulator material layers. Often, the conductive material is a metal, e.g., a copper-based material, which is plated onto insulator material layers and patterned by photolithographically removing deposited metal to form pads and traces. The substrate may be referred to as organic if organic material is combined with the copper-based material so as to provide thermal expansion characteristics close to those of the motherboard (not shown) and to improve reliability in board assembly.
In the example depicted in FIG. 1, the top two layers 24 and 26 and the bottom two layers 28 and 30 of the substrate 20 are formed by a lamination process from a thin resin material. The middle layer 32 located between the two top layers 24 and 26 and the two bottom layers 28 and 30 is called the core layer and is made of conventional printed circuit board material. The middle layer 32 includes middle layer through holes (not shown) used for electrically coupling the two top layers 24 and 26 to the two bottom layers 28 and 30. During fabrication of the substrate, the top two layers 24 and 26, the bottom two layers 28 and 30, and the middle layer 32 are laminated together.
As illustrated in FIG. 1, the middle layer 32 includes metal-plated through holes 34 that are formed by mechanical drilling through the middle layer. Pads 36 are located at the opposing ends of each through hole. The top and bottom layers 24, 26, 28, and 30 include microvias 38 which are formed by laser drilling the top two layers 24 and 26 and bottom two layers 28 and 30. Therefore, the various layers 22 of the substrate require multiple processing steps to do both mechanical and laser drilling. Also, each of the microvias 38 in the top two layers 24 and 26 and the bottom two layers 28 and 30 requires a separate laser drilling step. So, the total cost to fabricate both the through holes and microvias increases as the total number of mechanical and laser drilling steps increases.
Microvia interface pads 40 are coupled to the microvias 38 in the substrate's top layers and bottom layers 24, 26, 28 and 30. Each microvia is electrically coupled to a metal-plated through hole 34 by means of a pad 36. Pads 42 are formed on the bottom surface 18 of the substrate 20 and are mechanically and electrically coupled to microvias in the bottom two layers 28 and 30 of the substrate. Ball Grid Array (“BGA”) solder balls 44 are coupled to the pads 42 on the bottom surface of the substrate. Typically, the pads on the bottom surface of the substrate are coupled via the BGA solder balls to corresponding pads (not shown) on the motherboard (not shown). Die interface pads 46 are also located on both the bottom and top surfaces 18 and 16 of the substrate for interfacing with the first semiconductor die 14 and a second semiconductor die 12, respectively. The die interface pads are mechanically and electrically coupled to microvias in both the top and bottom layers 24, 26, 28, and 30 of the substrate. Microvia interface pads are correspondingly located below the microvias in the substrate's top layer 24 and above the microvias in the substrate's bottom layer 30.
The first semiconductor die 14 is mechanically and electrically coupled to the bottom surface 18 of the substrate 20. Also, the second semiconductor die 12 is mechanically and electrically connected to the top surface 16 of the substrate. Metallic bumps 48 on the bottom surfaces 50 and 52 of both the first and second semiconductor dies 14 and 12, respectively, overlap with die interface pads 46 correspondingly positioned on the bottom surface 18 and top surface 16 of the substrate, respectively. Typically, the metallic bumps are connected to the die interface pads by solder, thus providing direct electrical coupling between each of the first and second semiconductor dies and the substrate. Thus, the substrate provides for a mechanical and electrical interface between the often densely packed metallic bumps on the bottom surfaces 50 and 52 of both the first and second semiconductor dies to the less-densely packed pads (not shown) on the motherboard (not shown).
FIG. 1 also illustrates underfill resin 54 deposited between the first semiconductor die 14 and the bottom surface 18 of the substrate 20 and between the second semiconductor die 12 and the top surface 16 of the substrate. The underfill resin is a thermosetting polymer compound that includes thermally conductive compounds and electrically insulating material. After curing, the underfill resin strengthens the mechanical interface between each of the first and second semiconductor dies and the substrate by diverting much of the shear stress applied to the first and second semiconductor dies, e.g., shear stress due to vibration, and stress from the difference in thermal expansion between the first and second semiconductor dies and the substrate, away from the solder joints that interconnect the first and second semiconductor dies to the substrate and distributing the stress across the entire multi-chip module configuration 10. Therefore, the underfill resin increases mechanical reliability by reducing the likelihood of the electrical interfaces between the first and second semiconductor dies and the substrate being compromised due to mechanical stresses and vibration. The underfill resin also helps to dissipate heat from the semiconductor dies to the substrate.
Multi-chip module configurations 10 often include decoupling capacitors (not shown) that are used to reduce simultaneous switching noise (“SSN”). Since it is necessary to keep the loop inductance to the decoupling capacitors low, the distance between a semiconductor die 12 and 14 and the decoupling capacitors should be as short as possible. Therefore, the decoupling capacitors are often positioned on the surface of the substrate 20 that opposes the surface of the substrate to which the semiconductor die is coupled. The decoupling capacitors are electrically coupled to the semiconductor die by means of vias and traces (not shown) included in the substrate.
As stated above, the multi-chip module configuration 10 of FIG. 1 offers the benefit of improved electrical performance. However, the first semiconductor die 14, or decoupling capacitor (not shown), coupled to the bottom surface 18 of the substrate 20 likely will contact the surface (not shown) of the motherboard (not shown) when the multi-chip module is connected to the motherboard. The first semiconductor die or decoupling capacitor likely will contact the motherboard because the height of the BGA solder balls 44 are typically only 0.4 to 0.6 millimeter in height while the first semiconductor die or decoupling capacitor is typically greater than 0.7 millimeter in height.
In order to avoid this height differential problem, a column grid array (“CGA”) (not shown), typically 1.5 to 2.0 millimeters in height can be used instead of BGA solder balls 44 to couple the multi-chip module 10 to the motherboard (not shown). If a CGA is coupled to the bottom surface 18 of the substrate 20, the first semiconductor die 14 or decoupling capacitor (not shown) will not contact the surface (not shown) of the motherboard. However, installation of a CGA is complicated by the need for specialized installation equipment that is not widely available.
Another possible solution to the height differential problem is to glind the first semiconductor die 14, and thus, reduce the thickness of the first semiconductor die. However, the process of glinding the first semiconductor die is costly. Also, the glinding process cannot be applied to decoupling capacitors (not shown) because glinding would result in the removal of a portion of the multiple layers of ceramic and conductors that form each decoupling capacitor.
An additional possible solution to the height differential problem is to use thin decoupling capacitors. However, thin decoupling capacitors are typically costly in comparison to regular decoupling capacitors.
A further possible solution to the height differential problems is to fabricate a recess (not shown) or hole (not shown) in the motherboard (not shown) to accommodate the first semiconductor die 14 or decoupling capacitor (not shown). However, adding a recess or hole in the motherboard disadvantageously removes surface area from the motherboard that could be used for routing traces (not shown) or configuring vias below the first semiconductor die and/or decoupling capacitors.
An additional disadvantage associated with the multi-chip module configuration 10 of FIG. 1 is that the underfill resin 54 spreads out from under the first and second semiconductor dies 14 and 12, and away from the first and second semiconductor dies as the underfill resin is deposited between the first and second semiconductor dies, and the substrate 20. The spread of the underfill resin can extend up to 2 to 3 millimeters away from the first and second semiconductor dies. Because of the spread of the underfill resin, pads 42 for interfacing with BGA solder balls 44 cannot be located in the region of the substrate nearest the first and second semiconductor dies. As such, the dimensions of the substrate must be increased to leave margin space for the estimated spread of the underfill resin, which disadvantageously results in increased material cost in fabricating the substrate. Also, the increased separation between the first and second semiconductor dies and the BGA solder ball interface with the motherboard (not shown) disadvantageously counter acts the benefits associated with having shortened electrical connections between the first and second semiconductor dies and the motherboard.
Therefore, there is a need for a multi-chip module configuration 10 which prevents the semiconductor dies 12 and 14 or decoupling capacitors (not shown) coupled to the bottom surface 18 of the substrate 20 from contacting the motherboard (not shown) without the need of a column grid array (not shown), the need to glind the semiconductor dies, or the need to remove a portion of the motherboard. Also, there is a need for a multi-chip module configuration that has a fewer number of microvias 38 that are costly to fabricate. In addition, there is a need for a multi-chip module configuration that limits the spread of the underfill resin 54, and thus, provides greater surface area on the substrate for locating pads 42 and allows for locating pads 42 closer to the semiconductor die.